1.58 Bits: The End of Matrix Multiplication?

For decades, "Compute" has been synonymous with "Matrix Multiplication."

Whether it's training a ResNet in 2015 or iterating on GPT-5 in 2026, the fundamental bottleneck has always been W * X. We multiply high-precision floating-point weights by high-precision activations, billions of times per second.

This approach is powerful, but it's also incredibly wasteful.

The Floating Point Tax

Standard LLMs traditionally ran on FP16 (16-bit floating point) or BF16 (Brain Floating Point). That means every single parameter in a 70B model requires 16 bits of memory bandwidth to move, and expensive energetic computations to multiply.

To put that in perspective:

• FP16: 16 bits per weight
• INT8: 8 bits per weight (Quantized)
• INT4: 4 bits per weight (Aggressive Quantization)

Even at INT4, we are still performing multiplications. But what if we could stop multiplying entirely?

Enter the Ternary Era (1.58 Bits)

The BitNet b1.58 architecture proposes a radical shift. Instead of a spectrum of values, every weight in the neural network can only exist in three states:

• -1
• 0
• 1

In information theory, a system with 3 states holds approximately log2(3) ≈ 1.58 bits of information. Hence the name.

Why This Changes Physics

When your weights are , Matrix Multiplication (W * X) becomes Matrix Addition.

1. If W = 1, you just add X.
2. If W = -1, you subtract X.
3. If W = 0, you do nothing (sparsity).

You no longer need expensive floating-point multipliers (FPMs) in your hardware. You just need adders. This reduces energy consumption by orders of magnitude and strictly aligns memory access with compute.

Pareto Dominance

The craziest part? BitNet b1.58 matches full-precision LLaMA models in perplexity and downstream tasks.

It turns out that "precision" was a crutch. Models don't need 16-bit granularity to reason; they just need scale. By stripping away the precision, we can fit significantly larger models into the same memory footprint.

The Hardware Horizon

This isn't just a software trick; it's a hardware roadmap.

Current GPUs (H100, Blackwell) are optimized for FP16/FP8 tensor ops. They are technically "overqualified" for 1-bit inference. We are likely to see a new class of LPUs (Language Processing Units) designed strictly for integer addition, capable of running 100B+ parameter models on watts of power, not kilowatts.

The age of Matrix Multiplication is ending. The age of Integer Addition has begun.